Supermicro X7DB8+

Supermicro X7DB8+ ... provides the performance and feature set required for dual processor-based servers with configuration options optimized for communications, presentation, storage, computation or database applications. The 5000P (Blackford) chipset supports a single or dual Intel 64-bit dual core processor(s) with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P (Blackford) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXH).

The 5000P (Blackford) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333 MHz data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3GB/sec.) The MCH chipset connects up to 16 Fully Buffered DIMM modules, providing a total memory bandwidth of 25.5 GB/s for DDR2 533, and 32.0 GB/s for DDR2 667. The MCH chipset also provides three x8 PCI-Express and one x4 ESI interface to the ESB2. In addition, the 5000P (Blackford) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.