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Supermicro X7DVL-iThe chipset consists of the 5000V (Blackford-VS) Memory Controller Hub (MCH), and the Enterprise South Bridge 2 (ESB2). The 5000V (Blackford-VS) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64- bit wide, 1333 MHz data bus that transfers data at 10.7 GB/sec. The MCH chipset connects up to six Fully Buffered DIMM modules, providing a total memory size of up to 16 GB. The MCH chipset also provides one x8 PCI-Express interface to the ESB2. In addition, the 5000V (Blackford-VS) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing. |
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